master's thesis
Programming model of arithmetic-logic unit in a microprocessor

Goran Toth (2015)
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Computer Engineering and Automation
Chair of Computer Engineering
Metadata
TitleProgramski model aritmetičko-logičke jedinice mikroprocesora
AuthorGoran Toth
Mentor(s)Željko Hocenski (thesis advisor)
Ivan Vidović (thesis advisor)
Abstract
U ovom diplomskom radu upotrebom VHDL-a dizajniran je programski model 8-bitne aritmetičko-logičke jedinice mikroprocesora. Za dizajniranje i verifikaciju programskog modela, korišten je Xilinx ISE 14.7 programski paket te razvojni sustav Nexys 3. Realizirana je 21 različita operacija (aritmetičke operacije, logičke operacije, operacije pomaka i operacije usporedbe). Simulacija je provedena za niz testnih slučajeva koji su pokazali ispravan rad. Za potrebe testiranja modela implementiranog na razvojni sustav, dizajnirano je testno sučelje koje omogućava unos podataka putem tipkovnice i prikaz rezultata na 7-segmentnim pokaznicima. Implementirani model je testiran korištenjem istih testnih slučajeva kao za simulaciju i na taj način je dokazan ispravan rad.
Keywords8-bit arithmetic logic unit VHDL FPGA Nexys 3
Parallel title (English)Programming model of arithmetic-logic unit in a microprocessor
Committee MembersŽeljko Hocenski (committee chairperson)
Ivan Aleksi (committee member)
Tomislav Keser (committee member)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Lower level organizational unitsDepartment of Computer Engineering and Automation
Chair of Computer Engineering
PlaceOsijek
StateCroatia
Scientific field, discipline, subdisciplineTECHNICAL SCIENCES
Computing
Process Computing
Study programme typeuniversity
Study levelgraduate
Study programmeGraduate University Study Programme in Computer Engineering
Academic title abbreviationmag.ing.comp.
Genremaster's thesis
Language Croatian
Defense date2015-07-14
Parallel abstract (English)
This diploma thesis is describing a model design of a microprocessors 8-bit arithmeticlogic unit using VHDL. Xilinx ISE 14.7 software package is used for designing and verification of the program model. Nexys 3 development platform is used for implementation. 21 different operations are designed, like arithmetic operations, logic operations, shift operations and comparisons. The simulation was carried out for a number of test cases that showed proper operation. A interface that enables data entry via the keyboard was designed for testing purposes of the model implemented on the development system. The result is displayed on a 7-segment dispay unit. The implemented model was tested using the same test cases as the simulation and the results are showing correct model operation.
Parallel keywords (Croatian)8-bitna aritmetičko-logička jedinica VHDL FPGA Nexys 3
Resource typetext
Access conditionOpen access
Terms of usehttp://rightsstatements.org/vocab/InC/1.0/
URN:NBNhttps://urn.nsk.hr/urn:nbn:hr:200:581127
CommitterAnka Ovničević