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doctoral thesis
UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2010. urn:nbn:hr:200:434320
Matić, Tomislav
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

Cite this document

Matić, T. (2010). UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA (Doctoral thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:434320

Matić, Tomislav. "UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA." Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2010. https://urn.nsk.hr/urn:nbn:hr:200:434320

Matić, Tomislav. "UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA." Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2010. https://urn.nsk.hr/urn:nbn:hr:200:434320

Matić, T. (2010). 'UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA', Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 14 March 2025, https://urn.nsk.hr/urn:nbn:hr:200:434320

Matić T. UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA [Doctoral thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2010 [cited 2025 March 14] Available at: https://urn.nsk.hr/urn:nbn:hr:200:434320

T. Matić, "UTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA", Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2010. Available at: https://urn.nsk.hr/urn:nbn:hr:200:434320

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TitleUTJECAJ KAŠNJENJA KOMPARATORA S HISTEREZOM NA SREDIŠNJU FREKVENCIJU ASINKRONOG SIGMA-DELTA MODULATORA
Title (english)The influence of the hysteresis comparator delay on the central frequency of an asynchronous sigma-delta modulator
AuthorTomislav Matić
MentorTomislav Švedek (mentor)
Committee memberSnježana Rimac-Drlje (predsjednik povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2010-05-18, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Universal decimal classification
(UDC)		621.3 - Electrical engineering
Abstract
U radu su opisane osnovne karakteristike sinkronog i asinkronog sigma-delta (ASD) modulatora i dan je pregled trenutnog stanja u području primjene sigma-delta (SD) modulatora. U svrhu usporedbe, opisane su osnovne razlike izmeñu sinkrone i asinkrone izvedbe SD modulatora. Provedena je analiza utjecaja vremena kašnjenja komparatora s histerezom na radne značajke ASD modulatora. Matematičkim proračunima, računalnom simulacijom i izvedenim mjerenjima na modelima pokazano je smanjenje... More središnje frekvencije zbog utjecaja vremena kašnjenja. Za smanjenje nepoželjnog utjecaja vremena kašnjenja na radne značajke ASD modulatora predložene su dvije metode. Prva metoda se zasniva na ograničenju izlaznog signala iz integratora, čime se ostvaruje povećanje izlazne frekvencije (metoda 1), dok se kod druge metode uvodi amplitudna modulacija napona pragova histereze koja izlazni signal integratora postavlja unutar vrijednosti proračunatih napona pragova histereze. Na temelju matematičkog modela ASD modulatora, za potrebe simulacije utjecaja vremena kašnjenja i metoda za poboljšanje (metoda 1 i metoda 2), kreiran je Simulink model u programskom alatu Matlab®. U Matlab okruženju simuliran je i sklop za pretvorbu 1- bitovnog ASD signala govornog pojasa (frekvencija do 4 kHz) u sinkroni PCM m-bitovni digitalni signal. U simulacijskom programu Multisim Analog Devices Edition simulacijski model ASD modulatora primijenjen je na pojačalo snage D klase na kojem je takoñer ispitana metoda 2. Za verifikaciju matematičkih modela mjerenjima izrañen je laboratorijski model ASD modulatora s mogućnošću primjene metode 1 i 2. Rezultatima mjerenja na laboratorijskom modelu ASD modulatora potvrñeno je poboljšanje radnih značajki ASD modulatora primjenom navedenih metoda. Na sklopu pojačala snage D klase izmjereno je ukupno harmonijsko izobličenje izlaznog signala. Dokazano je da se primjenom metode 2 faktor ukupnog harmonijskog izobličenja smanjuje u cijelom rasponu amplituda ulaznog signala. Less
Abstract (english)
The basics properties of the synchronous and asynchronous sigma-delta (ASD) modulators have been described and current state-of-art in sigma-delta modulation applications has been reported. For comparison, the major differences between synchronous and asynchronous SD modulators have been described. Analysis of hysteresis comparator propagation delay influence to the ASD modulator performances has been provided. The mathematical analysis, computer simulations and measurement... More results confirm the central frequency detoriation due to propagation delay influence. For propagation delay compensation two methods have been proposed. The first method is based on limitation of the integrator output voltage (method 1), which increses ASD central frequency, while second method introduce hysteresis threshold voltage amplitude modulation which keeps the integrator output voltage within calculated hysteresis threshold levels. Based on the mathematical model of the ASD modulator, for simulation purposes of the propagation delay influence and the proposed method for propagation delay compensation (method 1 and method 2), Simulink model in Matlab® has been created. Matlab implementation of the A/D converter circuit for 1-bit ASD signal to synchronous PCM m-bit digital word for voice-band applications has also been proposed. Using Multisim Analog Devices Edition, simulation model of ASD modulator has been applied to class-D power amplifier for method 2 verification. For measurement results, the ASD modulator ciruit has been implemented with possibility for method 1 and method 2 application. The measuerment results on the ASD circuit confirm the mathematical analysis for the propagation delay influence and compensation method contributions which improve ASD modulator performances. For ASD modulator application in class-D power amplifier, total harmonic distorsion has been measured. It has been shown that method 2 implementation reduces total harmonic distorsion of output signal for full range of input signal amplitudes. Less
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:434320
Promotion2010-05-18
Study programmeTitle: Postgraduate doctoral study programme; specializations in: branch Power Engineering and Communications, branch Informatics
Course: branch Informatics
Study programme type: university
Study level: postgraduate
Academic / professional title: doktor/doktorica znanosti, područje tehničkih znanosti, polje elektrotehnika (doktor/doktorica znanosti, područje tehničkih znanosti, polje elektrotehnika)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
RepositoryFaculty of Electrical Engineering, Computer Science and Information Technology Osijek
Created on2018-03-07 15:42:21
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